This application is related to Korean Application No. 2000-79189, filed Dec. 20, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly, to integrated circuit capacitors and methods of manufacturing integrated circuit capacitors.
Ferroelectric substances may be used as dielectric layer materials in ferroelectric capacitors that are integrated in semiconductor memory devices. The ferroelectric substance exhibits voluntary polarization throughout a range of temperatures without an external electric field. Moreover, if a reverse electric field is applied to the ferroelectric substance, its polarized state can be inverted from one direction to an opposite direction. The ferroelectric substance has hysteresis characteristics according to the direction and size of the applied electric field. Ferroelectric random access memory (FRAM) devices utilize the hysteresis characteristics of the ferroelectric substance to achieve non-volatile performance characteristics.
A difficult problem associated with the manufacture of a ferroelectric capacitor has been the infiltration of hydrogen into ferroelectric materials during various etching processes and insulation layer forming processes. This infiltration of hydrogen can deteriorate the hysteresis characteristics of the ferroelectric material within the capacitor and degrade its non-volatile performance.
FIGS. 1 and 2 are cross-sectional views illustrating a conventional method of manufacturing a ferroelectric capacitor of a semiconductor device. Referring to FIG. 1, a first metal layer 40 (for a lower electrode layer of a ferroelectric capacitor) is formed on a lower interlayer dielectric layer 20 placed on a semiconductor substrate 10. The first metal layer 40 is connected to an impurity region in the semiconductor substrate via a contact plug 30 that penetrates the lower interlayer dielectric layer 20. Next, a ferroelectric layer and a second metal layer are sequentially formed on the first metal layer 40. The second metal layer is used for forming an upper electrode layer. The second metal layer and the ferroelectric layer are sequentially patterned to form a second metal layer pattern 60 and a ferroelectric layer pattern 50. Next, an oxide layer 70 is formed so as to be used as an etching mask in patterning the first metal layer 40. Conventionally, a phosphosilicate glass (PSG) layer is used as the oxide layer 70. Alternatively, a titanium nitride (TiN) layer may be used instead of the oxide layer 70.
Referring to FIG. 2, a first metal layer pattern 45 is formed by partially removing the first metal layer 40 using the oxide layer 70 as an etching mask. Next, a barrier layer 80 covering the first metal layer pattern 45 and the oxide layer 70 is formed. A TiO2 layer 81 and an Al2O3 layer 82 may be used as the barrier layer 80. In some cases, only the TiO2 layer 81 is used. Next, an upper interlayer dielectric layer 90 is formed on the barrier layer 80.
In the method for manufacturing a ferroelectric capacitor as described above, the oxide layer 70, having a relatively low hydrogen content, is used as an etching mask and the barrier layer 80, which includes a TiO2 layer 81 and an Al2O3 layer 82, is formed before formation of the upper interlayer dielectric layer 90. The oxide layer 70 and the barrier layer 80 operate to inhibit the characteristics of the ferroelectric layer pattern 50 from deteriorating due to penetration of hydrogen. However, because the oxide layer 70 may contain some hydrogen, hydrogen may infiltrate into the ferroelectric layer pattern 50. Also, there are frequently problems associated with the formation of the barrier layer 80. For example, in the event the TiO2 layer 81 is used alone, a high temperature thermal treatment process is typically required for enhancing the dielectric characteristics of the layer. During the thermal treatment process, however, a metal barrier layer (not shown) placed between the first metal layer pattern 40 and the underlying contact plug 30 may be oxidized and the contact resistance of the contact plug 30 may increase. To inhibit the increase in contact resistance, a dual layer consisting of the TiO2 layer 81 and the Al2O3 layer 82 should be used as the barrier layer 80 and in this case, a low temperature thermal treatment process may be performed on the barrier layer 80 after the TiO2 layer 81 is formed. However, in a step for forming a via hole in a peripheral circuit region, which is typically performed after formation of a ferroelectric capacitor, the size of the via hole may be reduced due to a difference in etching selectivity between the barrier layer 80 and an adjacent dielectric layer (not shown). Accordingly, the contact resistance in the peripheral circuit region may increase. To solve this problem, an additional process for removing the barrier layer 80 in the peripheral circuit region, particularly, the TiO2 layer 81, typically must be performed.
Methods of forming integrated circuit capacitors having dielectric layers therein that comprise ferroelectric materials, include the use of protective layers to block the infiltration of hydrogen into the ferroelectric material. By blocking the infiltration of hydrogen, the hysteresis characteristics of the ferroelectric materials can be preserved. According to one embodiment of the present invention, an integrated circuit capacitor is provided that comprises a semiconductor substrate and a lower capacitor electrode on the semiconductor substrate. A capacitor dielectric layer that comprises a ferroelectric material, is provided on the lower capacitor electrode. An upper capacitor electrode is also provided on the capacitor dielectric layer. In order to inhibit degradation of the ferroelectric characteristics of the capacitor dielectric layer, a protective layer is utilized to cover the capacitor dielectric layer. In particular, the protective layer is formed to encapsulate the upper capacitor electrode and the capacitor dielectric layer. The protective layer preferably includes a material that is substantially free of hydrogen and has a chemical and/or physical structure that blocks transfer (e.g., diffusion) of hydrogen therethrough. The protective layer may also have a thickness of greater than about 50 xc3x85, in order to further inhibit transfer of hydrogen from outside the protective layer to the underlying capacitor dielectric layer. The protective layer may comprise a metal oxide selected from the group consisting of Al2O3, TiO2, SiO2, ZrO2 and CeO2. The ferroelectric material may also comprise one or more of the following materials: SrTiO3, BaTiO3, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, SrBi2Ta2O9, (Pb, La)(Zr, Ti)O3 and Bi4Ti3O12. To achieve high oxidation resistance and low electrical resistance, the lower and upper capacitor electrodes preferably comprise a platinum-group metal layer, a platinum-group metal oxide layer or a composite of a platinum-group metal layer and a platinum-group metal oxide layer.
Methods of forming integrated circuit capacitors according to embodiments of the present invention include forming an interlayer dielectric layer on a semiconductor substrate and then sequentially forming a first electrode layer on the interlayer dielectric layer, a capacitor dielectric layer comprising a ferroelectric material on an upper surface of the first electrode layer and a second electrode layer on the capacitor dielectric layer. A step is then performed to pattern the second electrode layer as an upper capacitor electrode and pattern the capacitor dielectric layer as a capacitor dielectric. These patterning steps may cause the upper surface of the first electrode layer to be exposed.
The upper capacitor electrode and the capacitor dielectric are then encapsulated by depositing a protective layer on the upper surface of the first electrode layer and on the upper capacitor electrode and the capacitor dielectric. The protective layer comprises a material that is substantially free of hydrogen and has a chemical and/or physical structure that blocks transfer of hydrogen therethrough. Following formation of the protective layer, the protective layer and the first electrode layer are patterned to define a lower capacitor electrode and expose an upper surface of the interlayer dielectric layer. The step of depositing the protective layer may include an atomic layer deposition process. The encapsulating step may also be preceded by the step of annealing the capacitor dielectric at a temperature in a range between about 400xc2x0 C. and 500xc2x0 C. The encapsulating step may also be followed by the step of annealing the capacitor dielectric at a temperature in a range between about 400xc2x0 C. and 500xc2x0 C., however, this annealing step may be omitted if a prior annealing step has been performed.